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AR# 36968

LogiCORE CPRI v3.1 - Release Notes and Known Issues for 12.1


This Answer Record contains the Release Notes for the LogiCORE CPRI v3.1 Core, released in the ISE 12.1, and includes the following:

  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:


New Features

  • ISE 12.1 software support
  • Designed to version 4.1 (2009-02-18) of the CPRI specification
  • Support added for 4.915Gbps and 6.144Gbps line rates
  • Support added for GMII based Ethernet interface
  • Support added for user defined HDLC rates
  • Support added for vendor specific negotiation
  • Support added for 614Mbps in Virtex-6 LXT and SXT family devices

Resolved Issues

  • None

Known Issues

  • LogiCORE IP CPRI v3.1 is in pre-production stage (not fully hardware validated) on Virtex-6 and Spartan-6 device platforms.
  • The CPRI core defaults to using a 122.88 MHz reference clock when a design is generated for Virtex-6 and 6 Gig support is not included. CPRI operation at speeds of 2.4Gbps and above might require a different reference clock selection. Please read device errata anduser guides, or contact Xilinx for guidance on selecting the correct reference clock.
AR# 36968
Date Created 01/18/2011
Last Updated 02/11/2013
Status Active
Type General Article
  • CPRI