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AR# 36969

LogiCORE IP CPRI - Release Notes and Known Issues

Description

This answer record contains the Release Notes for the LogiCORE IP CPRI Core and includes the following:

  • New Features
  • Device Support
  • Resolved Issues
  • Known Issues
  • Release notes for previous versions of the core

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.

For CPRI core Vivado version, refer to (Xilinx Answer 54473).

Solution

LogiCORE IP CPRI v6.1

Update

The core has been updated for the 14.4/2012.4 versions of the design tools.

New Features

ISE Design Suite

  • ISE 14.4 design tools support
  • Support added for the four byte data path in 6.144 Mb/s capable cores.

Vivado Design Suite

  • Vivado 2012.4 design tools support
  • Support added for the four byte data path in 6.144 Mb/s capable cores
  • Block level of the design released as the top level in the Vivado tools

Device Support

ISE Design Suite

The following device families are supported by the core for this release:

Operation at line rates up to 3072.0 Mb/s supported in:

  • All 7 series devices
  • Virtex-6 devices
    • Virtex-6 CXT/LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT
  • Spartan-6 devices
    • Spartan-6 (Speed Grade -3) LXT
  • Virtex-5 devices
    • Virtex-5 LXT/SXT/TXT/FXT (LX30T or larger)

Operation at line rates up to 4915.2 Mb/s supported in:

  • All 7 series devices
  • Virtex-6 devices
    • Virtex-6 LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT

Operation at line rates up to 6144.0 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -1/-2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -1/-2/-3)
    • Not supported on wire bond packages
  • Artix-7 devices
    • Artix-7 (Speed Grade -2 and higher)
  • Zynq devices
    • Zynq (Speed Grade -1/-2/-3)
  • Virtex-6 devices
    • Virtex-6 (Speed Grade -2 and higher) LXT/SXT/HXT

Operation at line rates up to 9830.4 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -2/-3)
    • Not supported on wire bond packages
  • Zynq devices
    • Zynq (Speed Grade -2/-3)

CPRI cores supporting 6144.0 Mb/s will use a four byte datapath in -1 and -2L speedgrade Kintex-7, Virtex-7 and Zynq-7000 devices. This is to enable the use of the four-byte internal transceiver& datapath which is required to run at speeds over 5Gb/s in these devices. All cores supporting 9830.4 Mb/s and those implemented on Artix-7 devices also use a four byte datapath. See the Virtex-7 and Kintex-7 FPGA data sheets for more information. Contact Xilinx to ensure your chosen device will operate correctly.

Vivado Design Suite

The following device families are supported by the core for this release:

Operation at line rates up to 4915.2 Mb/s supported in:

  • All 7 series devices

Operation at line rates up to 6144.0 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -1/-2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -1/-2/-3)
    • Not supported on wire bond packages
  • Artix-7 devices
    • Artix-7 (Speed Grade -2 and higher)

Operation at line rates up to 9830.4 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -2/-3)
    • Not supported on wire bond packages

CPRI cores supporting 6144.0 Mb/s will use a four byte datapath in -1 and -2L speedgrade Kintex-7, Virtex-7 and Zynq-7000 devices. This is to enable the use of the four-byte internal transceiver datapath which is required to run at speeds over 5Gb/s in these devices. All cores supporting 9830.4 Mb/s and those implemented on Artix-7 devices also use a four byte datapath. See the Virtex-7 and Kintex-7 FPGA data sheets for more information. Contact Xilinx to ensure your chosen device will operate correctly.

Known Issues

ISE Design Suite

The following are known issues for v6.1 of this core at time of release:

  • A modified reset sequence is required for cores implemented on Artix-7 devices (GTPE2 transceivers) and Virtex-7 devices (GTHE2 transceivers). This reset sequence must be implemented in the core transceiver wrapper files. Please refer to (Xilinx Answer 53561) for Artix-7 devices and (Xilinx Answer 53779) for Virtex-7 devices.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 FPGA is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.

Vivado Design Suite

The following are known issues for v6.1 of this core at time of release:

  • A modified reset sequence is required for cores implemented on Artix-7 devices (GTPE2 transceivers) and Virtex-7 devices (GTHE2 transceivers). This reset sequence must be implemented in the core transceiver wrapper files. Please refer to (Xilinx Answer 53561) for Artix-7 devices and (Xilinx Answer 53779) for Virtex-7 devices.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.

LogiCORE CPRI v5.2

Update

The device support section has been updated for the 14.3/2012.3 versions of the software tools. The -1 speedgrade Kintex-7 and Virtex-7 FPGAs have now been added to the list of devices that require a four-byte internal transceiver path for operation at 6144.0 Mb/s.

New Features

ISE Design Suite

  • ISE 14.2 design tools support
  • Support added for Artix-7 and Zynq devices
  • Speed change DRP writes and reads now implemented in the FPGA fabric for 7 series devices

Vivado Design Suite

  • 2012.2 design tools support
  • Support added for Artix-7 and Zynq devices
  • Speed change DRP writes and reads now implemented in the FPGA fabric for 7 series devices

Device Support

ISE Design Suite

The following device families are supported by the core for this release: 

Operation at line rates up to 3072.0 Mb/s supported in:

  • All 7 series devices
  • Virtex-6 devices
    • Virtex-6  CXT/LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT
  • Spartan-6 devices
    • Spartan-6 (Speed Grade -3) LXT
  • Virtex-5 devices
    • Virtex-5 LXT/SXT/TXT/FXT (LX30T or larger)

Operation at line rates up to 4915.2 Mb/s supported in:

  • All 7 series devices
  • Virtex-6 devices
    • Virtex-6 LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT

Operation at line rates up to 6144.0 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -1/-2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -1/-2/-3)
    • Not supported on wire bond packages
  • Artix-7 devices
    • Artix-7 (Speed Grade -2 and higher)
  • Zynq devices
    • Zynq (Speed Grade -1/-2/-3)
  • Virtex-6 devices
    • Virtex-6 (Speed Grade -2 and higher) LXT/SXT/HXT

Operation at line rates up to 9830.4 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -2/-3)
    • Not supported on wire bond packages
  • Zynq devices
    • Zynq (Speed Grade -2/-3)

CPRI cores supporting 3072.0 Mb/s, 4915.2 Mb/s and 6144.0 Mb/s use a two-byte internal transceiver datapath in all devices other than Artix-7. This can limit support for -1, -2L, -2G and -2LE Virtex-7 and Kintex-7 devices. For more information, see the Virtex-7 and Kintex-7 FPGA data sheets. Cores supporting 9830.4 Mb/s and those implemented on Artix-7 devices use a four-byte internal transceiver datapath. Contact Xilinx to ensure your chosen device will operate correctly.


Vivado Design Suite

The following device families are supported by the core for this release:

Operation at line rates up to 4915.2 Mb/s supported in:

  • All 7 series devices

Operation at line rates up to 6144.0 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -1/-2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -1/-2/-3)
    • Not supported on wire bond packages
  • Artix-7 devices
    • Artix-7 (Speed Grade -2 and higher)

Operation at line rates up to 9830.4 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -2/-3)
    • Not supported on wire bond packages

CPRI cores supporting 3072.0 Mb/s, 4915.2 Mb/s and 6144.0 Mb/s use a two-byte internal transceiver datapath in all devices other than Artix-7. This can limit support for -1, -2L, -2G and -2LE Virtex-7 and Kintex-7 devices. For more information, see the Virtex-7 and Kintex-7 FPGA data sheets. Cores supporting 9830.4 Mb/s and those implemented on Artix-7 devices use a four-byte internal transceiver datapath. Contact Xilinx to ensure your chosen device will operate correctly.

Known Issues

ISE Design Suite

The following are known issues for v5.2 of this core at time of release:

  • LogiCORE IP CPRI v5.2 is in pre-production stage (not fully hardware validated) on Virtex-7 and Kintex-7 device platforms.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 FPGA is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.
  • The GUI allows the use to select line rates of up to 4.915 Gb/s on a Kintex-7 part using speed grade -2L. The maximum line rate on these speed grade parts is now 3.072Gb/s.

Vivado Design Suite

The following are known issues for v5.2 of this core at time of release:

  • LogiCORE IP CPRI v5.2 is in pre-production stage (not fully hardware validated) on Virtex-7 and Kintex-7 device platforms.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.
  • The GUI allows the use to select line rates of up to 4.915 Gb/s on a Kintex-7 part using speed grade -2L. The maximum line rate on these speed grade parts is now 3.072Gb/s.

LogiCORE IP CPRI v5.1

New Features

ISE Design Suite

  • ISE 14.1 design tools support
  • UTRA-FDD IQ module extended to 32-bit data path and 48 channels for9830.4 Mb/s capable cores
  • E-UTRA IQ module support added
  • Support added for the ORI interface
  • Dynamically switchable operation between master and slave added
  • Virtex-7 and Kintex-7 PLLE2 support added
  • Kintex-7 BUFH used to route recovered clock
  • Increased reference clock frequency support in Kintex-7, Virtex-7and Virtex-6 devices
  • GMII interface supported for 4915.2 Mb/s capable cores
  • Support added for GTHE2 transceivers

Vivado Design Suite

  • 2012.1 design tools support

Device Support

ISE Design Suite

The following device families are supported by the core for this release.

Operation at line rates up to 3072.0 Mb/s supported in:

  • All 7 series devices
  • Virtex-6 devices
    • Virtex-6 CXT/LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT
  • Spartan-6 devices
    • Spartan-6 (Speed Grade -3) LXT
  • Virtex-5 devices
    • Virtex-5LXT/SXT/TXT/FXT
    • (LX30T or larger)

Operation at line rates up to 4915.2 Mb/s supported in:

  • All 7 series devices
  • Virtex-6 devices
    • Virtex-6 LXT/SXT/HXT
    • Virtex-6 Lower Power (-1L) LXT/SXT

Operation at line rates up to 6144.0 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -1/-2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -1/-2/-3)
    • Not supported on wire bond packages
  • Virtex-6 devices
    • Virtex-6 (Speed Grade -2 and higher) LXT/SXT/HXT

Operation at line rates up to 9830.4 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -2/-3)
    • Not supported on wire bond packages

CPRI cores supporting 3072.0 Mb/s, 4915.2 Mb/s and 6144.0 Mb/s use two-byte internal transceiver datapath. This can limit support for -1, -2L, -2G and -2LE Virtex-7 and Kintex-7 devices. See the Virtex-7 and Kintex-7 FPGA data sheets for more information. Cores supporting 9830.4 Mb/s use a 4-byte internal transceiver datapath. Contact Xilinx to ensure your chosen device will operate correctly.

Vivado Design Suite

The following device families are supported by the core for this release.

Operation at line rates up to 4915.2 Mb/s supported in:

  • All 7 series devices

Operation at line rates up to 6144.0 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -1/-2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -1/-2/-3)
    • Not supported on wire bond packages

Operation at line rates up to 9830.4 Mb/s supported in:

  • Virtex-7 devices
    • Virtex-7 (Speed Grade -2/-3)
  • Kintex-7 devices
    • Kintex-7 (Speed Grade -2/-3)
    • Not supported on wire bond packages

CPRI cores supporting 3072.0 Mb/s, 4915.2 Mb/s and 6144.0 Mb/s use a two-byte internal transceiver datapath. This can limit support for -1, -2L, -2G and -2LE Virtex-7 and Kintex-7 devices. See the Virtex-7 and Kintex-7 FPGA data sheets for more information. Cores supporting 9830.4 Mb/s use a four-byte internal transceiver datapath. Contact Xilinx to ensure your chosen device will operate

Resolved Issues

ISE Design Suite

  • Require to increase UTRA-FDD IQ module channels from 32
    As CPRI 4.1 has a line rate of 9830.4 Mb/s for series 7 the number of channels supported should be increased appropriately
    CR 589637
  • GMII interface option now supported on 4915.2 Mb/s cores
    CR 591304
  • Have external ports for Status signals
    Modify the core to bring out the status signals L1 reset, SDI, RAI, LOS, LOF. rather than accessing them via the management interface
    CR 594185
  • 10G GTXE2_COMMON and RXOUT_DIV settings are incorrect in CPRI v4.1
    In version 4.1 of the CPRI core QPLL_FBDIV is set to 64 and the PicoBlaze processor in the CPRI core sets RXOUT_DIV to 2. This is incorrect as QPLL_FBDIV should be 32 and RXOUT_DIV should be 1.
    CR 628844 and AR 45939
  • Request to support Ref Clk of 122.88 MHz for CPRI 5G
    The current CPRI IP Core v 4.1 does not support Reference Clock of 122.88 MHz for CPRI 5G (4.915 Gb/s). Request that we add support for this frequency.
    CR 630085
  • Enhancement Request to have a combined Master/Slave core for CPRI
    The customer would like the ability to change between Master and Slave CPRI core after power up. Currently only Master or Slave option is provided at build time from the CORE Generator tool.
    CR 630543 correctly.

Known Issues

ISE Design Suite

The following are known issues for v5.1 of this core at time of release:

  • LogiCORE IP CPRI v5.1 is in pre-production stage (not fully hardware validated) on Virtex-7 and Kintex-7 device platforms.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 FPGA is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.

Vivado Design Suite

The following are known issues for v5.1 of this core at time of release:

  • LogiCORE IP CPRI v5.1 is in pre-production stage (not fully hardware validated) on Virtex-7 and Kintex-7 device platforms.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.

LogiCORE IP CPRI v4.1 Rev 1

(Xilinx Answer 45939) - A REV1 Patch Update to enable the operation of the CPRI core at speeds up to 9.830 Gb/s on general engineering samples of the Virtex-7 and Kintex-7 devices.

New Features

  • Support for Kintex-7 and Virtex-7 general ES

Device Support

  • Operation at line rates up to 3072.0 Mb/s supported in:
    • Virtex-5 LXT device families, XC5VLX30T and larger, with speedgrade of -1 or higher
    • Virtex-5 SXT device families, XC5VSX35T and larger, with speedgrade of -1 or higher
    • Virtex-5 FXT device families, XC5VFX30T and larger, with speedgrade of -1 or higher
    • Virtex-5 TXT device families with speedgrade of -1 or higher
    • Virtex-6 LXT, SXT and CXT device families with speedgrade of -1/-1L or higher
    • Spartan-6 LXT device families with speedgrade of -3 or higher
    • Virtex-7 device families with speedgrade of -1 or higher
    • Kintex-7 device families with speedgrade of -1 or higher
  • Operation at line rates up to 4915.2 Mb/s supported in:
    • Virtex-6 LXT and SXT device families, with speedgrade of -1
    • Virtex-7 and Kintex-7 device families with speedgrade of -1 in non FFG type packages
  • Operation at line rates up to 6144.0 Mb/s supported in:
    • Virtex-6 LXT and SXT device families, with speedgrade of -2 or higher
    • Virtex-7 and Kintex-7 device families with speedgrade of -1 or higher in FFG type packages
    • Virtex-7 and Kintex-7 device families with speedgrade of -2 or higher in non FFG type packages
  • Operation at line rates up to 9830.4 Mb/s supported in:
    • Virtex-7 and Kintex-7 device families with speedgrade of -2 or higher in FFG type packages

Resolved Issues
(Xilinx Answer 44010) - GTXE2_COMMON Use Model Change

Known Issues

  • LogiCORE IP CPRI v4.1 is in pre-production stage (not fully hardware validated) on Virtex-7 and Kintex-7 FPGA platforms.
  • Operation at 9.8 Gb/s on Virtex-7 and Kintex-7 devices is supported using a direct connection to a XFP using the XFI electrical specification or SFP+ optical module using SFI electrical specification.
  • (Xilinx Answer 39430) Virtex-6 GTX Transceiver - Delay Aligner Errata and Work-around

7 Series Known Issues
(Xilinx Answer 44011) - IBUFDS_GTE2 Use Model Change
(Xilinx Answer 44012) - TXOUTCLK and RXOUTCLK Ports Restrictions
(Xilinx Answer 44215) - Should the transceiver transmit and receive elastic buffers should be enabled?

LogiCORE IP CPRI v4.1

New Features

  • ISE 13.1 design tools support
  • Support added for version 4.2 of the CPRI specification
  • Support added for Virtex-7 and Kintex-7 device families
  • Support added for 9.830 Gb/s line rate
  • AXI4-Lite management interface option added
  • Example design expanded with data generators and monitors
  • Extra cycle of latency added in CDC FIFO to improve timing performance

Device Support

  • Operation at line rates up to 3072.0 Mb/s supported in:
    • Virtex-5 LXT device families, XC5VLX30T and larger, with speedgrade of -1 or higher
    • Virtex-5 SXT device families, XC5VSX35T and larger, with speedgrade of -1 or higher
    • Virtex-5 FXT device families, XC5VFX30T and larger, with speedgrade of -1 or higher
    • Virtex-5 TXT device families with speedgrade of -1 or higher
    • Virtex-6 LXT, SXT and CXT device families with speedgrade of -1/-1L or higher
    • Spartan-6 LXT device families with speedgrade of -3 or higher
    • Virtex-7 device families with speedgrade of -1 or higher
    • Kintex-7 device families with speedgrade of -1 or higher
  • Operation at line rates up to 4915.2 Mb/s supported in:
    • Virtex-6 LXT and SXT device families with speedgrade of -1
    • Virtex-7 and Kintex-7 device families with speedgrade of -1 in non FFG type packages
  • Operation at line rates up to 6144.0 Mb/s supported in:
    • Virtex-6 LXT and SXT device families with speedgrade of -2 or higher
    • Virtex-7 and Kintex-7 device families with speedgrade of -1 or higher in FFG type packages
    • Virtex-7 and Kintex-7 device families with speedgrade of -2 or higher in non FFG type packages
  • Operation at line rates up to 9830.4 Mb/s supported in:
    • Virtex-7 and Kintex-7 device families with speedgrade of -2 or higher in FFG type packages

Resolved Issues

  • CR565276 - CPRI v3.1- Unconstrained paths
  • CR570274 - Constraint on recclk is unclear in docs and ucf
  • CR573232 - Coregen CPRI - BRAM FF is not on for less than 6G
  • CR578391 - Coregen CPRI - Add information about the coarse timer and how it changes to user guide and testbench
  • CR582127 - Coregen CPRI - UG447 and Figure 6-14 does not show the data after the basic frame first word changing
  • CR589566 - Disable delay aligner in Virtex-6 devices

Known Issues
(Xilinx Answer 40946) - What is the smallest Spartan-6 device that supports the dual core IP configuration?
(Xilinx Answer 42626) - Port Changes in GTXE2_Common wrapper to be released in ISE Design Suite 13.2
(Xilinx Answer 42819) - In the CORE Generator software, can the IP be targeted at the Virtex-7 XT device family?
(Xilinx Answer 42820) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"?
(Xilinx Answer 43764) - Where can I find EDK-based CPRI or CPRI multi-hop reference designs?
(Xilinx Answer 39430) - Virtex-6 FPGA GTX Transceiver - Delay Aligner Errata and Work-around

7 Series Known Issues
(Xilinx Answer 44010) - GTXE2_COMMON Use Model Change
(Xilinx Answer 44011) - IBUFDS_GTE2 Use Model Change
(Xilinx Answer 44012) - TXOUTCLK and RXOUTCLK Ports Restrictions
(Xilinx Answer 44215) - Should the transceiver transmit and receive elastic buffers should be enabled?

LogiCORE IP CPRI v3.2 New Features

  • ISE 12.2 design tools support
  • Support added for 4.915 Gb/s support on -1 speedgrade Virtex-6 devices

Resolved Issues

  • None

Known Issues

LogiCORE IP CPRI v3.2 is in pre-production stage (not fully hardware validated) on Virtex-6 and Spartan-6FPGAplatforms.

(Xilinx Answer 43764) - Where can I find EDK-based CPRI or CPRI multi-hop reference designs?
(Xilinx Answer 37455) - Why does TXRESETDONE never get asserted and why does the core fail to synchronize or get stuck with stat_code = 0010 in Virtex-6 FPGA?
(Xilinx Answer 39992) - GTX Transceiver: Delay Aligner Errata and Work-around
(Xilinx Answer 40541) - How is the IP affected by the Spartan-6 PK block RAM Issue?
(Xilinx Answer 40946) - What is the smallest Spartan-6 device that supports the dual core IP configuration?
(Xilinx Answer 43764) - Where can I find EDK-based CPRI or CPRI multi-hop reference designs?

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
45939 LogiCORE IP CPRI v4.1 - A Rev1 Patch Update to enable the operation of the CPRI core at speeds up to 9.830 bps on General ES of the Virtex-7 and Kintex-7 FPGA parts N/A N/A
44215 7 Series Integrated Wrapper for LogiCORE CPRI - v4.1- Should the transceiver transmit and receive elastic buffers be enabled? N/A N/A
44012 7 Series Integrated Wrapper for LogiCORE CPRI - TXOUTCLK and RXOUTCLK Port Restrictions N/A N/A
44011 7 Series Integrated Wrapper for LogiCORE CPRI - IBUFDS_GTE2 Use Model Change N/A N/A
44010 7 Series Integrated Wrapper for LogiCORE CPRI - GTXE2_COMMON Use Model Change N/A N/A
43764 LogiCORE CPRI v3.2 - Where can I find EDK-based CPRI or CPRI multi-hop reference designs? N/A N/A
42820 LogiCORE CPRI v4.1 - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" N/A N/A
42819 LogiCORE CPRI v4.1 - Within Core Generator can the IP be targeted at the Virtex-7 XT family? N/A N/A
42626 7 Series Integrated Wrapper for LogiCORE CPRI - Port Changes in GTXE2_Common Wrapper in ISE Design Suite 13.2 N/A N/A
42621 Logicore CPRI v4.1- How can I speed up simulation of the negotiation of the line speed between two CPRI cores? N/A N/A
42113 LogiCORE CPRI v4.1 - How do you implement a chain topology between a CPRI slave and a CPRI master? N/A N/A
40946 LogiCORE CPRI v3.2/v4.1 - What is the smallest Spartan-6 that supports the dual core IP configuration with different line rates? N/A N/A
40796 LogiCORE IP CPRI v3.2 - How long is stat_alarm asserted? N/A N/A
40228 Logicore CPRI v 3.x - Is the GMII interface available for all line rates? N/A N/A
40021 LogiCORE CPRI v3.2 - What is the Ethernet Interface FIFO depth and width? N/A N/A
39992 LogiCORE CPRI v3.2 - GTX Transceiver: Delay Aligner Errata and Work-around N/A N/A
37455 Logicore CPRI v3.2 - Why does TXRESETDONE never get asserted and why does core fail to synchronize or get stuck with stat_code = 0010 in Virtex-6? N/A N/A

Associated Answer Records

AR# 36969
Date Created 08/18/2010
Last Updated 04/30/2014
Status Archive
Type Release Notes
IP
  • CPRI