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AR# 36971

LogiCORE IP OBSAI - Release Notes and Known Issues

Description

This answer record contains the Release Notes for the LogiCORE OBSAI Core and includes the following: 

  • New Features
  • Device Support
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

LogiCORE IP OBSAI has been discontinued. Please see the Following PDN:

http://www.xilinx.com/support/documentation/customer_notices/XCN16013_v1%200.pdf

Solution

LogiCORE IP OBSAI v5.1

New Features

  • ISE 13.1 software support
  • Support for Virtex-7 and Kintex-7 devices (Pre-Production status)
  • AXI-Lite Control/Status Management interface added
  • Various RP3-01 Interoperability changes
  • Rx RTT address filtering removed
  • Tx Addresses independently controllable for O&M message types
  • Modulo-Index rule control for RP3-01 messaging
  • CDC FIFO initial fill level selectable (Master core only)
  • CDC FIFO max depth increased to 512 byte (Master core only)

Device Support

  • Operation at line rates up to 3072.0 Mb/s supported in:
    • Virtex-7 and  Kintex-7
    • Virtex-6 XC CXT/LXT/SXT/HXT/-1L
    • Spartan-6 XC LXT (Speed Grade -3 or higher)
    • Virtex-5 XC LXT/SXT/TXT/FXT
  • Operation at line rates up to 6144.0 Mb/s supported in:
    • Virtex-7 devices
    • Kintex-7 FFG device packages Speed Grade -1 or higher
    • SBG and FBG device packages Speed Grade -2 or higher
    • Virtex-6 XC CXT/LXT/SXT/HXT devices (Speed Grade -2 or higher)

Resolved Issues 

  • Disable delay aligner in Virtex-6 devices
  • Virtex-6 FPGA delay aligner fix requires BUFG in MMCM feedback path

Known Issues

  • LogiCORE IP OBSAI v5.1 is in a pre-production state (not fully hardware validated) on Virtex-7 and Kintex-7 FPGA platforms.
  • One extra BUFG is required in Virtex-6 devices relative to the figure stated in the data sheet due to CR591084 for the delay aligner.

(Xilinx Answer 42627) Port Changes in GTXE2_Common wrapper to be released in ISE 13.2 software
(Xilinx Answer 42817) Why does the Implement script fail with "ERROR:Xst:1817 - Invalid target device '7v285t'"?
(Xilinx Answer 42821) "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"?

7 Series FPGAs Known Issues

(Xilinx Answer 45965) What files need to be changed in ISE Design Suite 13.4 to support General Engineering Silicon v(GES) for Kintex-7 devices?
(Xilinx Answer 44408) What are the GTXE2_CHANNEL attribute updates?
(Xilinx Answer 44409) GTXE2_COMMON Use Model Change for BIAS_CFG
(Xilinx Answer 44410) IBUFDS_GTE2 Use Model Change
(Xilinx Answer 44411) TXOUTCLK and RXOUTCLK Ports Restrictions
(Xilinx Answer 44412) Should the transceiver transmit and receive elastic buffers be enabled?

LogiCORE IP OBSAI v4.2

New Features

  • ISE 12.2 software support
  • Production Status for Virtex-6 and Spartan-6 FPGA
  • OBSAI RP3 V4.2 specification support

Resolved Issues 

  • None

Known Issues

(Xilinx Answer 37454) Why does TXRESETDONE never get asserted and why does core fail to synchronize or assert stat_tx_frame_sync in Virtex-6 FPGA Core?
(Xilinx Answer 39993) GTX Transceiver - Delay Aligner Errata and Work-around
(Xilinx Answer 40542) How is the IP affected by the Spartan-6 FPGA PK block RAM Issue?

Linked Answer Records

Child Answer Records

AR# 36971
Date Created 07/23/2010
Last Updated 04/20/2016
Status Archive
Type Release Notes
IP
  • OBSAI