The built in block RAM and FIFO primitives in the Virtex-6 FPGA can be used to implement RAMs, ROMs, and FIFO blocks for a design.The block RAM and FIFO are optimized for performance and allow you to implementa RAM, ROM, or FIFO block in a design without requiring large amounts of fabric resources from slice logic.
The
Virtex-6 FPGA Memory Resources User Guide (UG363)provides additional details on the block RAM and FIFOs. It is recommended that you read through the user guides to familiarize yourself with its use and how they can be used in your design:
http://www.xilinx.com/support/documentation/user_guides/ug363.pdf In addition, the following Answer Recordsare useful in providing details on different ways to implement block RAMs and FIFO blocks in your code:
(Xilinx Answer 37183) - How to infer the use of Block RAM and FIFO primitives in your HDL code
(Xilinx Answer37184) - Using block RAM CORE Generator and FIFO CORE Generator to setup the blocks for use in HDL code