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AR# 36991 Virtex-6 FPGA Design Assistant - Details on using different clocking buffers

Description


The different clock buffers available in the Virtex-6 device family allow you to setup clock regions or control clock usage with an enable or select. This Answer Record contains information on where to find the documentation for each of the different clock buffers available in the Virtex-6 device family.
NOTE: This Answer Record is a part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963) Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution


The following buffers are available for use with your clocks in the Virtex-6 FPGA designs:
  • BUFIO
  • BUFR
  • BUFG/BUFGCTRL/BUFGMUX
  • BUFH

BUFIO/BUFR
The BUFIO/BUFR buffers are used for regional clocks that do not need to reach all regions of the device.They are typically used for clocking IOSERDES interfaces.If you would like additional information on how to use either of these two buffers, you can find this informationin theRegional Clocking Resources sectionof the Virtex-6 Clocking Resources Users Guide (UG362):
http://www.xilinx.com/support/documentation/user_guides/ug362.pdf

BUFG/BUFGCTRL/BUFGMUX
The BUFG/BUFGCTRL/BUFGMUX are used for Global clocks that need to reach logic throughout the entire device. You can only reach the BUFG buffers through a special Global Clock pin (GCLK pin). If you would like more information regarding how to use the BUFG buffers, you can find this informationin the Global Clocking Resources section of theVirtex-6 Clocking Resources Users Guide (UG362):
http://www.xilinx.com/support/documentation/user_guides/ug362.pdf

BUFH

The horizontal clock buffer (BUFH) is a buffer that drives a horizontal global clock tree spine in a single region. These buffers include a clock enable that can be used to dynamically turn the clock network on or off. This allows you to conserve power by giving you the ability to turn off regions of logic that are not in use. For more information on how to use the BUFH buffer, you can find this information in the Regional Clocking Resources section of theVirtex-6 Clocking Resources Users Guide (UG362):
http://www.xilinx.com/support/documentation/user_guides/ug362.pdf

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34979 Virtex-6 FPGA Design Assistant - Designing clocking structures in Virtex-6 FPGAs N/A N/A

Actions

AR# 36991
Date Created 08/26/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
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