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AR# 37005

12.3 Schematic - Instantiated Clocking Wizard core fails synthesis: ERROR:HDLCompiler:267


Whenimplementing a design containing aClocking Wizard core for a Spartan-6 (schematic) design,I get the followingerrors during Synthesis when the Project's Preferred Language is set to Verilog.

Synthesis Errors:

ERROR:HDLCompiler:267 - "C:\..\..\tl.vf" Line 64: Cannot find port clk_in1 on this module
ERROR:HDLCompiler:267 - "C:\..\..\tl.vf" Line 65: Cannot find port clk_out1 on this module
ERROR:HDLCompiler:267 - "C:\..\..\tl.vf" Line 66: Cannot find port clk_out2 on this module
ERROR:HDLCompiler:267 - "C:\..\..\tl.vf" Line 67: Cannot find port locked on this module


Port definitions created for the core symbol and passed to theschematic_name.vf file in lower case.

In the Verilog file (dcm2clk.v) and the core netlist generated by the Clocking Wizard, the port definitions are in UPPER case:

(* CORE_GENERATION_INFO = "clk_wiz_v1_5,clk_wiz_v1_5,{component_name=clk_wiz_v1_5,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false}" *)

module clk_wiz_v1_5
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED

In the Verilog file generated through the schematic flow (top.vf) the port definitions are in LOWER case:

dcm2clk XLXI_1 (.clk_in1(XLXN_1),

Since Verilog is case sensitive this is the cause of the errors in XST.

To work around this issue, do one of the following:
  • Modify the port definitions in the .vf file to UPPER case.
  • Change the View Functional Model language to VHDL
AR# 37005
Date Created 10/14/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 12.1