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AR# 37007

Design Assistant for PCI Express - Unsupported request bit not set when cfg_err_posted_n is deasserted and cfg_err_ur_n is asserted


When de-asserting cfg_err_posted_n and asserting cfg_err_ur_n to send a completion with a non-successful status, the unsupported request bit in the Device Status register output to the user on cfg_dstatus[3] is not set. However, if cfg_err_posted_n is asserted, the unsupported request bit is set.
NOTE:This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe.Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


A non-posted request that results as an unsupported request is treated as an Advisory Non-Fatal Error (ANFE) condition. See section of the PCI Base Specification v2.0. The Virtex-6, Spartan-6, and Virtex-5 Integrated Blocks do not support the Advanced Error Reporting (AER) capability, so following the flow diagram in section 6.2.5 (Table 6-2), if the uncorrectable error is an ANFE condition and since AER is not supported then the unsupported bit is not set.
A unsupported request for a posted packet is not considered an ANFE condition, so according to the flow diagram the UR bit is set.
Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 37007
Date Created 07/30/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LXT
  • Virtex-5 SXT
  • More
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Spartan-6 LXT
  • Less
  • Endpoint Block Plus Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )