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AR# 37014 Virtex-6 GTX Transceiver: ERROR:MapLib:1226 - GTXE1 - DRC Error when POWER_SAVE is set incorrectly

Description


In ISE software 12.2, DRC checks have been added to ensure that the recommendations in the Virtex-6 FPGA Errata are followed. This Answer Record discusses one such error:

"ERROR:MapLib:1226 - GTXE1
GenPCPURxXAUI.PCPUXAUI_IF/XAUIGEN.0.PortInf/PhyXAUI/xaui_block/gtx_wrapper_i/
gtx0_GTX312_WRAPPER_i/gtxe1_i has RX_BUFFER_USE set to TRUE and POWER_SAVE<5>
different than '1', which is invalid"

Solution


This error is specific to the attribute updates made by the Wizard for production silicon, specifically POWER_SAVE[5:4] = 2?b11 for cases where the TX phase alignment buffer and RX elastic buffer are used. This change does not impact the function of the MGT if the recommendations in the Virtex-6 Errata and (Xilinx Answer 35055) are followed, and are backward compatible with ES silicon.

To resolve this error, the POWER_SAVE attribute needs to be updated. If the TX buffer is used, set POWER_SAVE[4] = 1?b1 and if the RX buffer is used, set POWER_SAVE[5] = 1?b1. Running the Virtex-6 GTX Transceiver Wizard again generates the correct settings for your implementation.

Actions

AR# 37014
Date Created 07/27/2010
Last Updated 07/27/2010
Status Active
Type
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