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AR# 37038

Aurora 64b/66b - TX_DST_RDY_N deasserts 2 cycles after every 32 cycles


The Aurora 64B/66B core pauses the user interface by de-asserting TX_DST_RDY_N for 2 cycles after every 32 USER_CLK cycles.


The Gearbox in the GT needs a pause every 32 cycles to insert the extra bit into the data stream for 64b/66b encoding/decoding. This is explained in the Virtex-6 GTX User Guide (UG198) in the TX Gearbox Operating Modes section.
The TX_DST_RDY_N on the user LocalLink interface is the critical path gating the complete interface based on Auroras priority logic.
This signal is paused for 2 cycles instead of 1 on the user interface to meet the timing on the core. This slightly brings down the effective bandwidth of the core.
An enhancement CR has been filed on the core and is to be reviewed for a future release.
AR# 37038
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 TXT
  • Virtex-6 SXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Less
  • Aurora 64B/66B
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