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AR# 37042 Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed?

Description

When using the Virtex-6 x8 Gen 2 product, if the core trains to Gen 1 speeds, does the 128-bit user interface remain 128 bits?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

Solution

The x8 Gen 2 product always uses the full 128-bit interface regardless of what speed the link trains too. Also see (Xilinx Answer 36075) regarding information about packet straddling on the 128-bit interface.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36075 Design Assistant for PCI Express - 128-bit interface with packet straddling N/A N/A
36049 Design Assistant for PCI Express - TRN User Application Interface Questions N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A

Actions

AR# 37042
Date Created 08/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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