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AR# 37067

Virtex-6 FPGA Design Assistant - Using optimization features from third-party synthesis tools


The following Answer Record discusses how optimization features can be used from third-party synthesis tools to help optimize your design.
NOTE: This Answer Record is a part of the Xilinx Virtex-6 FPGASolution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


Some third-party synthesis tools such as SynplifyProhave optimization features that can help to improve performance with your design.For more information on synthesis tool settings that should be utilized,see theHDL Coding Practices to Accelerate Design PerformanceWhite Paper(WP231):
Following is a list of sections in this white paper that specifically mention the different synthesis tool settings:
  • "Maximize Block RAM Performance"
  • "Use of I/O Registers"
  • "Replicate Registers with High-Fanout"
  • "Nested If-Then-Else, Case Statements, and Combinatorial For-Loops"

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36986 Virtex-6 FPGA Design Assistant - Designing configurable logic structures in Virtex-6 FPGAs N/A N/A
AR# 37067
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
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