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AR# 37077

Logicore Peak Cancelation CFR (PC-CFR) v2.0 - Coefficients loading via configurable coefficients input ports


When loading a new coefficient via configurable coefficients input ports, how many clock cycles can SREG_AWVALID and SREG_WVALID be asserted?


SREG_AWVALID and SREG_WVALID can be asserted for only one clock cycle, you will meet memory collision errors if these valid signals are asserted fore more than one clock cycle.

Please see (Xilinx Answer 33760) for a detailed list of LogiCORE IP Peak Cancelation Crest Factor Reduction - Release Notes and Known issues

AR# 37077
Date Created 09/29/2010
Last Updated 09/29/2010
Status Active
Type General Article
  • Peak Cancellation Crest Factor Reduction(PC-CFR)