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AR# 37081

MIG Spartan-6 MCB - Calibrated Input Termination IBIS Simulation


This section of the MIG Design Assistant focuses onCalibrated Input Termination IBIS Simulation for Spartan-6 MCB designs.

Note: This Answer Record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


MIG can provide calibrated on-die input termination for DDR2 and DDR3 memory interfaces. When this option is selected, the mcb_soft_calibration module calibrates the input termination for the bidirectional memory interface signals dq, ldqs_p/n, udqs_p/n to an external 100 Ohm pull-up resistor on the RZQ pin. This results in an input termination value that is close to the UNTUNED_SPLIT_50 uncalibrated input termination.

To simulate the MCB interface using Calibrated Input Termination, you mustseparate write and read interfaces in the IBIS simulations and simulate them independently.

To simulate the input, use the SSTL15_IN50M_* model for DDR3 interfaces and the SSTL18_IN50M_* model for DDR2 interfaces.
To simulate the output, use only the driver model and exclude the input buffer mode.

Example: for a standard DDR3 interface on a Spartan-6 MCB with calibrated input termination selected and Vccaux = 2.5 Volts, you use the following models for the DQ/DQS interface:

  • To model the pin as a driver, you would use the SSTL15_II_LR_25 Model.
  • To model the pin as a receiver, you would use the SSTL15_IN50M_LR_25 Model.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
40867 MIG Spartan-6 MCB - Signal Integrity Simulation Using IBIS N/A N/A
40780 MIG Spartan-6 MCB - FPGA Input Termination Options N/A N/A
AR# 37081
Date Created 08/22/2011
Last Updated 02/27/2013
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • MIG