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AR# 37134

Spartan-6 - Why is INIT_B low after power-on?


The INIT_B pin is discovered low after powering on the board without sending any configuration data into theSpartan-6 device. The Spartan-6 FPGA Configuration User Guide (UG380) states that a low INIT_B indicates a CRC error.
What does it mean?
Either way, I can still correctly program the Spartan-6 device.


Spartan-6 FPGA has a configuration watchdog timer (CWDT)which isused to monitor detection of the sync word. The CWDT register stores the value of the number of clock cycles that the FPGA waits before the watchdog time-out (in which SYNCWORD is not received). The default is 64k clock cycles. CWDT cannot be disabled by the user.

If mode pins are set to 00 (Master SelectMAP/BPI)or 01 (Master Serial/SPI), the Spartan-6 device is the configuration master and it attempts to find the Sync Word while CWDT is running.If no Sync Word is detected within the specified time, INIT_B is pulled Low; reporting that no external config source (SPI or BPI or PROM) is detected.

If mode pins are set to 10 (Slave SelectMAP)or 11 (Slave Serial), the Spartan-6 device is a slave in configuration. INIT_B keeps High as the Spartan-6 device does not activelysearch forthe Sync Word.
AR# 37134
Date 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 12.2
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