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AR# 37155

LogiCORE DDS (Direct Digital Synthesizer) Compiler v4.0 - Why if I select Second Order Taylor Series is the core limited to 400 MHz?


Why if I select Second Order Taylor Series is the core limited  to 400 MHz?


The Second order Taylor Series configuration of the DDS, required when SFDR is greater than 120 dBs and the Phase Width is greater than or equal to  16 bits, is limited to 400 MHz operation on Virtex-6 FPGA. This is because of the use of read-first mode by the memory component xbip_bram18k_v2_1. However, this is a ROM and so can be configured to write first in order to enable 450 MHz operation.

INST "my_instance/BU3/U0/I_SINCOS.i_comp_eff.i_eff/SECOND_ORDER_A
M.I_BROM/i_synth_opt.i_synth/i_not_sandia.i_prim" WRITE_MODE_A="WRITE_FIRST";
INST "my_instance/BU3/U0/I_SINCOS.i_comp_eff.i_eff/SECOND_ORDER_A
M.I_BROM/i_synth_opt.i_synth/i_not_sandia.i_prim" WRITE_MODE_B="WRITE_FIRST";

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
29976 LogiCORE DDS (Direct Digital Synthesizer) Compiler - Release Notes and Known issues N/A N/A
AR# 37155
Date Created 10/22/2010
Last Updated 05/26/2014
Status Archive
Type Known Issues
  • Direct Digital Synthesizer