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AR# 37171

7 series, Virtex-6/-5/-4, Spartan-6 - How do you enable internal Differential Termination?


How do you enable Differential Termination for true differential input IOSTANDARDs?


You can enable internal DIFF_TERM inthree ways:

  • Enable DIFF_TERM in HDL Code. The Language Templates and device Libraries Guide contain the instantiation template for the IBUFDS/IBUFGDS which contains an attribute DIFF_TERM that is set to TRUE to enable the DIFF_TERM.

    For example VERILOG Instance:

    IBUFDS #(
    .DIFF_TERM("TRUE"), // Differential Termination
    .IOSTANDARD("DEFAULT") // Specify the input I/O standard
    ) IBUFDS_inst (
    .O(O), // Buffer output
    .I(I), // Diff_p buffer input (connect directly to top-level port)
    .IB(IB) // Diff_n buffer input (connect directly to top-level port)

    For example VHDL:

    IBUFDS_inst : IBUFDS
    generic map (
    DIFF_TERM => TRUE, -- Differential Termination
    IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
    port map (
    O => O, -- Buffer output
    I => I, -- Diff_p buffer input (connect directly to top-level port)
    IB => IB -- Diff_n buffer input (connect directly to top-level port)
  • Enable DIFF_TERM in UCF. The DIFF_TERM constraint syntax is documented in the Constraints Guide.

    For example:
    INST "IO block name" DIFF_TERM = "{TRUE|FALSE}" ;
  • For information on setting the attribute in the PlanAhead tool, see (Xilinx Answer 41668).

AR# 37171
Date 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Artix-7
  • More
  • Kintex-7
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Zynq-7000
  • Less