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AR# 37173

MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3


This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.6 released in ISE Design Suite 12.3 and contains the following information:
  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:

If you are looking for the MIG v3.61 release notes please to(Xilinx Answer 38951) v3.61 - Release Notes and Known Issues for ISE Design Suite 12.4.


General Information

MIG v3.6 is available through ISE Design Suite 12.3.

For a list of supported memory interfaces and frequencies for Spartan-3 Generation, Virtex-4, and Virtex-5 FPGA, see the MIG User Guide:

For a list of supported memory interfaces and frequencies for the Spartan-6 FPGA MCB, see the Spartan-6 FPGA Memory Controller User Guide:

For a list of supported memory interfaces and frequencies for Virtex-6 FPGA, see the Virtex-6 FPGA Memory Interface Solutions User Guide and Datasheet:

Software Requirements
  • Xilinx ISE Design Suite 12.3
  • Synplify D-2010.03 SP1 Support
  • 32-bit Windows XP
  • 32-bit Linux Red Hat Enterprize 4.0
  • 64-bit/32-bit Linux Red Hat Enterprize 4.0
  • 64-bit XP professional
  • 32-bit Vista business
  • 64-bit SUSE 10
  • 64-bit/32-bit Linux Red Hat Enterprize 5.0 support
  • 64-bit Windows Vista support
  • 32-bit SUSE 10 support
New Features,

  • ISE Design Suite 12.3 software support
  • Support of AXI interface for Virtex-6 DDR2/3 SDRAM designs
  • Support of AXI interface for all Spartan-6 designs
  • Provided flexibility to select the Master Bank in Virtex-6 Single Controller designs
  • Synplicity support for Defense Grade Virtex-6 and Spartan-6 parts
  • Improved the verification of BUFR and BUFIO constraints of DDR2/3 SDRAM designs of Virtex-6
  • Support of 2Gb LPDDR part for Spartan-6 designs
Resolved Issues
MIG User Guide
  • Provided trace length requirements for Q/CQ and D/K relationship for Virtex-6 QDR II+ SRAM designs in UG406
    • CR 564807
  • Provided an explanation as to how to modify the traffic generator for the CMD_PATTERN in UG416
    • CR 558915
  • Provided notes on how to drive IDELAYCTRL with a PLL in UG406
    • CR 566497
  • Provided more information on Class selection for various families (Spartan-3, Virtex-4 and Virtex-5) in UG086
    • CR 565600 and CR 566503

MIG Tool
  • Provided Warning instead of Error message when VRP/VRN pins are used as GPIO in Spartan-3 designs
    • CR 563777
  • Provided the flexibility in verification of Master Banks in Multi Controller designs
    • CR 561727
  • Provided the PROHIBIT constraint on the non-used DQSN/UDQSN pins in UCF of Spartan-6 designs
    • CR 552374

  • (Xilinx Answer 36554) MIG v3.5, Virtex-6 Multi-Controller Designs - Failure occurs in MAP when controllers require separate REFCLK frequencies (200 and 300MHz)
  • (Xilinx Answer 36477) MIG v3.5, Virtex-6 DDR3/QDRII+ - ERROR:Place:911 - CONFIG DCI_CASCADE = "34,35" is not a valid constraint.
  • (Xilinx Answer 36573) MIG v3.5, Virtex-6 DDR3/QDRII+ - Cannot place System Clock in between DCI Cascade Master/Slave banks
  • Improved the default bank selections efficiently for QDR II+ SRAM designs
    • CR 542962
  • Reset signal (DDR3_Reset) voltage standard changed to LVCMOS15 from SSTL15
    • CR 564152

  • (Xilinx Answer 37704) MIG v3.5 Spartan-6 MCB - Calibration does not complete (calib_done=0) when C_SIMULATION=FALSE
    • CR573416
  • (Xilinx Answer 34046) MIG v3.3-3.5, Spartan-6 LPDDR - Calibrated and Un-Calibrated Input Termination features not supported
  • (Xilinx Answer 36575) MIG v3.0-3.5, Spartan-6 MCB - Refresh period is too large
  • PROHIBIT constraints added on unused DQSN/UDQSN pins in UCF in case of single-ended DQS designs
    • CR 552374
  • Added 2Gb memory parts support for DDR3 designs
    • CR 568940
  • Added new parameter to differentiate between input and memory clock
    • CR 570186
  • Reset signal (DDR3_Reset) voltage standard changed to LVCMOS15 from SSTL15
    • CR 564152

Spartan-3 Generation

  • (Xilinx Answer 36553) MIG v3.5, Spartan-3A DSP DDR SDRAM - MAP fails on MIG output design when synthesized using Synplicity
Known Issues

Virtex-6 MIG Designs
(Xilinx Answer 37968) MIG v3.6 Virtex-6 DDR2/DDR3 - Additional calibration stage (CLKDIV Calibration Stage) added to calibrate the timing of the BUFIO to BUFR transfer
(Xilinx Answer 37861) MIG v3.6, Virtex-6 DDR3 - Multi-Controller VHDL designs may exhibit data errors in simulation when targeting an RDIMM
(Xilinx Answer 37863) MIG v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error
(Xilinx Answer 37997) MIG v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices
(Xilinx Answer 38083) MIG v3.6, Virtex-6 DDR3 - Multi-Controller Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16
(Xilinx Answer 38104) MIG v3.6, Virtex-6 - GUI does not allow AXI RDIMM data width selection.
(Xilinx Answer 38111) The Design Notes include incorrect statements regarding rank support and hardware testbench support.
(Xilinx Answer 38125) MIG v3.6, Virtex-6 DDR2/DDR3 - MIG v3.6, Virtex-6 DDR2/DDR3 - comments in the UCF are incorrect.

Spartan-6 FPGA MCB
(Xilinx Answer 36550) MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design
(Xilinx Answer 38000) MIG v3.6 Spartan-6 MCB - WARNING:sim - ProjectMgmt - Circular Reference: work:Module|mux

Spartan-3 Generation MIG Designs
(Xilinx Answer 38105) MIG v3.3, Spartan-3A DDR2 - Failed MAXDELAY constraint on "dqs_int_delay_in" net for XC3S400a-FT256 devices

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 37173
Date Created 09/21/2010
Last Updated 05/20/2012
Status Active
Type Release Notes
  • ISE Design Suite - 12.3
  • MIG