What constraints do I need to implement the AXI_Ethernet core in my EDK system?
Solution
The recommended constraints for the AXI based Ethernet systems targeting Virtex-6 and Spartan-6 devices are available in this answer record. The pin locations are specific to the board layout and hence have not been included here.
The archives also contain an example of the MHS instantiation of the AXI_Ethernet core with the physical interface and target device. The "readme.txt" included in the archive contains a more detailed description of the files.
These constraints have been tested on specific development boards and some attributes such as IDELAY, IDELAYCTRL, and GTP/GTX locations can change in custom implementations.