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AR# 37180

Design Assistant for PCI Express - How is the core configured to have Extended Tag Field Support?

Description


How is the core configured to have Extended TagField Support?
NOTE: This Answer Record is part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536).TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution


The user must check the "Extended Tag Field" check box during customization in the CORE Generator softwarein order to set the "Extended Tag Field Supported" bit (bit 5) in the Device Capability Register. If this bit is set, the host can then set the "Extended Tag Field Enable" bit in the Device Control Register. Once this bit is set, the user can generate TLPs with eight bit tags. Otherwise,five bit tags must be used.
For more information, see sections 7.8.3 and 7.8.4 of the PCI Express Base Specification.
Revision History
10/12/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 37180
Date Created 10/13/2010
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Virtex-5 Integrated Endpoint Block
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Endpoint Block Plus Wrapper for PCI Express
  • More
  • Endpoint Block Wrapper for PCI Express
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
  • Less