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Xilinx High-Speed Serial I/O Solution Center



The High Speed Serial I/O (HSSIO) Solution Center is a resource to help answer any questions related to the Xilinx Multi-Gigabit Transceivers. Whether implementation, board level, or any other aspect of the design process, the Solution Center aims to guide you to the correct information.

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Documentation

High-Speed Serial Transceiver Documentation

This answer record contains a list of all of the documentation that is relevant to High Speed Serial Applications utilizing the Xilinx Multi-Gigabit Transceivers, including user guides, data sheets, errata with transceiver-related items, application notes, and white papers.

7 Series

Virtex-6

Spartan-6

Virtex-5

Virtex-4

Virtex-II Pro

Application Notes

Application notes for the Xilinx RocketIO and High-Speed Transceivers fall into one of three categories:

1) Serial Digital Interface Application Notes

2) Serial IO Application Notes

3) Protocol Specific Application Notes:

White Papers

White papers for the Xilinx RocketIO and High-Speed Transceivers fall into one of two main categories:

1) Serial Digital Interface White Papers

2) Protocol Specific White Papers:

Relevant Errata

7 Series

Virtex-6

Spartan-6

Virtex-5

Virtex-4 FXT

Virtex-II Pro X


Design Advisories

Design Advisories for High Speed Serial Transceivers

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

Design Advisory Answer Records discuss new issues that are relevant to designs currently in progress. Users can be informed of relevant HSSIO design advisories by signing up for specific silicon families in the Xilinx Alert Notification System. To update your Xilinx Alert Notification Preferences, go to: http://www.xilinx.com/support/myalerts.

Design Advisory Master Answer Records
(Xilinx Answer 51456) Design Advisory Master Answer Record for Artix-7 FPGA
(Xilinx Answer 42944) Design Advisory Master Answer Record for Virtex-7 FPGA
(Xilinx Answer 42946) Design Advisory Master Answer Record for Kintex-7 FPGA
(Xilinx Answer 34856) Design Advisory Master Answer Recordfor Spartan-6 FPGA
(Xilinx Answer 34565) Design Advisory Master Answer Recordfor te Virtex-6 FPGA


Top Issues

High-Speed Serial Transceivers - Top Issues

This answer record lists some of the top and known issues for high-speed serial transceivers across FPGA families that designers might want to know.

Transceiver Family-Specific Known Issues

(Xilinx Answer 47852) 7 Series FPGA GTP Transceiver Known Issues and Answer Record List
(Xilinx Answer 41613) 7 Series FPGA GTX/GTH Transceiver Known Issues and Answer Record List
(Xilinx Answer 38596) Virtex-6 FPGA GTH Transceiver Known Issues and Answer Record List
(Xilinx Answer 33475) Virtex-6 FPGA GTX Transceiver Known Issues and Answer Record List
(Xilinx Answer 33487) Spartan-6 FPGA GTP Transceiver Known Issues and Answer Record List
(Xilinx Answer 31458) Virtex-5 FPGA GTX RocketIO Transceiver Answer Record List
(Xilinx Answer 24367) Virtex-5 FPGA GTP RocketIO Transceiver Answer Record List
(Xilinx Answer 21004) Virtex-4 FPGA RocketIO Transceiver Answer Record List
(Xilinx Answer 21006) Virtex-II Pro FPGA RocketIO Transceiver Answer Record List

Top Issues

7 Series

(Xilinx Answer 47443) Design Advisory for 7 Series FPGAs GTH Transceiver Power-Up/Power-Down
(Xilinx Answer 47817) Design Advisory for the Kintex-7 and Virtex-7 GTX Transceiver Power-Up/Power-Down
(Xilinx Answer 51017)7 Series FPGA GTP Transceiver Power-Up/Power-Down
(Xilinx Answer 47328) 7 Series GTX-Loopback mode known limitations
(Xilinx Answer 43482) 7 Series GTXTransceivers -Reset requirements upon configuration
(Xilinx Answer 45598) 7 Series FPGA GTX/GTH Transceivers -Quad Usage Priority Information
(Xilinx Answer 47331) 7 Series FPGA GTX/GTH Transceivers - No Power Sequencing Requirement for MGTAVTT/MGTVCCAUX
(Xilinx Answer 50299) 7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores - Support for GTX Transceivers in Zynq Devices
(Xilinx Answer 50890) 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2
(Xilinx Answer 46048) 7 Series FPGAs Transceivers Wizard - What silicon revisions are supported by different Wizard or ISE design tool versions?
(Xilinx Answer 43244) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon
(Xilinx Answer 45410) 7 Series FPGA GTX Transceivers - Initial ES to General ES Silicon GTX Migration
(Xilinx Answer 47128) Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers
(Xilinx Answer 51369) Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 43339) 7 Series FPGA GTX Transceiver Software Use Model Changes

Virtex-6

(Xilinx Answer 40902) Virtex-6 FPGA GTH Transceiver - Updates for Production HXT; attributes and initialization sequences
(Xilinx Answer 41464) Virtex-6 HXT Devices - How do I Identify ES vs. Production Silicon?
(Xilinx Answer 42987) Virtex-6 FPGA GTH Transceiver - Reference clock phase noise mask
(Xilinx Answer 38564) Virtex-6 GTX - Variation in analog power supply voltage while powering up or down transceivers
(Xilinx Answer 38506) Virtex-6 FPGA GTX Transceiver - Reference clock phase noise mask
(Xilinx Answer 39430) Virtex-6 GTX Transceiver - Delay aligner errata and work-around
(Xilinx Answer 35055) Virtex-6 FPGA GTX Transceiver - Automatic Macro Insertion for Unused GTX Transceivers
(Xilinx Answer 34191) Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon
(Xilinx Answer 35681) Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert
(Xilinx Answer 34192) Virtex-6 GTX Transceiver Wizard - Oversampling rate update for production silicon
(Xilinx Answer 34028) Virtex-6 GTX Transceiver - Instantiating a dummy transceiver to allow for correct calibration

Spartan-6

(Xilinx Answer 43154) Spartan-6 FPGA GTP Transceiver - Reference clock phase noise mask
(Xilinx Answer 35776) Spartan-6 GTP Transceiver - Recommended PMA_CDR_CFG settings for improved CDR performance
(Xilinx Answer 35237) Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines
(Xilinx Answer 35434) Spartan-6 GTP Transceiver - Updates for production silicon

Virtex-5

(Xilinx Answer 30915) Virtex-5 GTP RocketIO - MGTAVCC Power recommendations for unused tiles between calibration resistor and instantiated tiles
(Xilinx Answer 31968) Virtex-5 GTX RocketIO - Rate change implementation steps

Software

(Xilinx Answer 22088) 7.1i MAP - "WARNING:PhysDesignRules:367 - The signal <DESIGN_MODULE/TXN> is incomplete"

General

(Xilinx Answer 37954) High Speed Serial Transceivers - Powering unused transceivers