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AR# 37183

Virtex-6 FPGA Design Assistant - How to infer the use of block RAM and FIFO primitives in your HDL code

Description


The following Answer Record points you to information on how to infer block RAM and FIFO primitives in your HDL code.
NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution


Block RAMs and FIFOs can be inferredif implemented correctly in your HDL code.The XST User Guide (UG627) discusses in detail how you need to code in order to infer a block RAM or FIFO in your design:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_2/xst.pdf

Specifically, the "RAMs and ROMs Hardware Description Language (HDL) Coding Techniques" section provides details on how to infer RAMs and ROMs built using block RAM in your design.
In addition, theHDL Coding Practices to Accelerate Design Performance White Paper (WP231)provides additional information on coding techniques that can be used to optimize performance of Block RAM in your design.Refer tothe "Maximize Block RAM performance" section:
http://www.xilinx.com/support/documentation/white_papers/wp231.pdf

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36987 Virtex-6 FPGA Design Assistant - Designing block RAM and FIFO structures in Virtex-6 FPGAs N/A N/A
AR# 37183
Date Created 08/27/2010
Last Updated 03/04/2013
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less