UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37184

Virtex-6 FPGA Design Assistant - Using block RAM CORE Generator and FIFO CORE Generator to setup the blocks for use in HDL code

Description


ThisAnswer Record provides information on how to setup block RAM or FIFOs with IP generated CORE Generator software.
NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution


If you need to directly instantiate a block RAM or FIFO block directly into your design, the CORE Generator tool can be used. For more information on how to use the block RAM Generator or FIFO Generator IP cores, refer to the corresponding data sheets listed below for each IP core:
Once you generate either of these cores in the CORE Generator tool, the cores include an instantiation template (.veo file for verilog, .vho file for vhdl) that you can use to instantiate the core into your HDL code.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36987 Virtex-6 FPGA Design Assistant - Designing block RAM and FIFO structures in Virtex-6 FPGAs N/A N/A
AR# 37184
Date Created 08/27/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less