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AR# 37201

FIFO Generator 6.3 - Crashes when creating a 36 x65K core


In FIFO Generator whena customercreates a design with a common clock or an Independent clock, the core shows huge BRAM usage (over a million).


ERROR:coreutil:576 - An error occurred while running Java. Please examine the console or coregen log file for a specific IP related error.
For more information please search the Xilinx Answers Database for this error: http://www.xilinx.com/support

ERROR:coreutil - XST has returned an error: ERROR:ip - min_area_algorithm: For the configured RAM size, the number of block RAMs used exceeds the maximum number of 18KB block RAMs in the Spartan-6

Solution: Currently we do not have any solution for this issue. The issue primarily related to BMG (Block Memory Generator), and this issue will not be seen in FIFO once BMG has the fix.
AR# 37201
Date 05/19/2012
Status Active
Type Known Issues
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.2
  • FIFO Generator
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