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AR# 37212 Virtex-6 FPGA Design Assistant - Troubleshoot Common Clocking Problems

Description


The Answer Record helps guide you to solutions to common problems with Clocking in Virtex-6 FPGA designs.
NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGASolution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution


See the information regarding the Virtex-5 PLL in theClocking Debug Guide for Virtex-6 MMCM troubleshooting:
http://www.xilinx.com/support/troubleshoot/clocking_debug.htm
If you still have a problem after running through the suggestions, open a WebCase with Xilinx Technical Support:
http://www.xilinx.com/support/clearexpress/websupport.htm

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37211 Virtex-6 FPGA Design Assistant - Troubleshooting N/A N/A

Actions

AR# 37212
Date Created 08/27/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
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