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AR# 37213 Virtex-6 FPGA Design Assistant - Troubleshoot common fabric problems

Description

This Answer Record helps guide you to solutions to common problems with the fabric resources in Virtex-6 FPGAdesigns.

NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGASolution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution


Select from the following list of common fabric related problems. Each Answer Record helps guide you to a solution.
If you still have a problem after running through the suggestions, open up a WebCase through Xilinx Technical Support:
http://www.xilinx.com/support/clearexpress/websupport.htm

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33209 11.x XST - "WARNING:Xst:2971 - This design infers one or more latches/registers with both an active asynchronous set and reset..." N/A N/A
34120 11.3 Virtex-6/-5 Pack - Inversion not pushed into Output FF input N/A N/A
32987 11.1 MAP, Virtex-6/ Virtex-5/ Spartan-6 - What options are available that allow two SRL16s to be combined into one LUT Complex? N/A N/A
34352 11.4 Virtex-6 MAP - Constant optimization of LUT6_2 inputs mishandled leading to errors N/A N/A
34164 Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software N/A N/A
37211 Virtex-6 FPGA Design Assistant - Troubleshooting N/A N/A

Actions

AR# 37213
Date Created 08/27/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
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