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AR# 37214 Virtex-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems

Description

This Answer Record helps guide you to solutions to common problems with the block RAM and FIFO resources in Virtex-6 FPGA designs.

NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

Solution

Select from the followinglist of common block RAM or FIFO related problems.Each Answer Record helps guide you to a solution:

Refer to the suggestions below for suggestions that can be used to help debug issues relating to the Virtex-6 Block RAM or FIFO

  • Refer to the Virtex-6 Memory Resources User Guide and verify that your usage of the Block RAM or FIFO block is a legal configuration (http://www.xilinx.com/support/documentation/user_guides/ug363.pdf)
  • Run a behavioral simulation of the design and verify proper functionality of the Block RAM or FIFO.
  • Run a post-par timing simulation and verify proper functionality. If a failure occurs here, your design may not be properly constrained.
  • Also check the timing report to ensure all control signals are properly constrained and synchronous. Check the Xilinx Timing Solution Center (Xilinx Answer 40832) for more information on timing in a Xilinx FPGA design.
  • Insert ChipScope into your design and probe all the ports of the FIFO or Block RAM. ChipScope can be used to probe parts of your design in fabric and view these signals in real time in hardware. For more information on ChipScope, please visit the ChipScope product page athttp://www.xilinx.com/tools/cspro.htm

If you still have a problem after running through the suggestions and debug techniques, pleaseopen up a WebCase through Xilinx Technical Support:
http://www.xilinx.com/support/clearexpress/websupport.htm

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
37218 Virtex-6 FPGA Design Assistant - Issues related to the block RAM and FIFO Core generator available in the CORE Generator software N/A N/A
33224 Virtex-6 FPGA FIFO - First read after reset is incorrect N/A N/A
34859 Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap N/A N/A
21870 Virtex-II/-II Pro/-4/-5/-6, 7 Series FPGA Block RAM - Do the setup and hold times of the ADDRESS inputs need to be met, even if the output is unused and WE is deasserted? N/A N/A
37211 Virtex-6 FPGA Design Assistant - Troubleshooting N/A N/A
15130 Virtex-II/Virtex-II Pro DCM - To use variable phase shift, a BitGen option must be set and phase shift must be in the positive range N/A N/A
14425 Virtex-II/-II Pro/-4/-5 FPGA DCM - Resetting after configuration is strongly recommended for a DCM that is configured with external or internal feedback (VHDL/Verilog) N/A N/A
10129 Virtex-E/Spartan-IIE - Power supply sequencing of VCCO and VCCINT N/A N/A
9586 Virtex/-E - How long must a reset be applied to a DLL in order to reset it? N/A N/A
31832 13.x Constraints - Is there a way to globally set IOSTANDARD constraints and not have to set it for each individual I/O? N/A N/A
29845 Spartan-II, Spartan-IIE, Virtex, Virtex-E - CLKDV output of the DLL does not toggle N/A N/A
12010 Virtex II - What is the difference between Cycle-Cycle Jitter and Period Jitter (as discussed in the Virtex-II data sheet)? N/A N/A

Actions

AR# 37214
Date Created 08/27/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
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