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AR# 37214

Virtex-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems


This Answer Record helps guide you to solutions to common problems with the block RAM and FIFO resources in Virtex-6 FPGA designs.

NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


Select from the followinglist of common block RAM or FIFO related problems.Each Answer Record helps guide you to a solution:

Refer to the suggestions below for suggestions that can be used to help debug issues relating to the Virtex-6 Block RAM or FIFO

  • Refer to the Virtex-6 Memory Resources User Guide and verify that your usage of the Block RAM or FIFO block is a legal configuration (http://www.xilinx.com/support/documentation/user_guides/ug363.pdf)
  • Run a behavioral simulation of the design and verify proper functionality of the Block RAM or FIFO.
  • Run a post-par timing simulation and verify proper functionality. If a failure occurs here, your design may not be properly constrained.
  • Also check the timing report to ensure all control signals are properly constrained and synchronous. Check the Xilinx Timing Solution Center (Xilinx Answer 40832) for more information on timing in a Xilinx FPGA design.
  • Insert ChipScope into your design and probe all the ports of the FIFO or Block RAM. ChipScope can be used to probe parts of your design in fabric and view these signals in real time in hardware. For more information on ChipScope, please visit the ChipScope product page athttp://www.xilinx.com/tools/cspro.htm

If you still have a problem after running through the suggestions and debug techniques, pleaseopen up a WebCase through Xilinx Technical Support:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

AR# 37214
Date Created 08/27/2010
Last Updated 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less