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AR# 3722

A1.4/F1.4 Map - XC5200 combinatorial latch implemented wrong in a f5_mux.


Design has a latch that feeds logic. The output of the
latch goes to a and2b2 in design it is implemented as a
and2b1, the feed from the latch is not inverted


This problem is fixed in the latest M1.4 Core Tools Patch available on the Xilinx
Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip

AR# 3722
Date Created 03/31/1998
Last Updated 04/25/2000
Status Archive
Type General Article