If a completion is lost and the fatal error bit is not set, this might be the issue. If a completion is lost and the fatal error bit is set, this is most likely not the problem. In that case, it is more likely a receiver buffer overflow condition. The user application can monitor the fatal error bit on the cfg_dstatus[2] output from the wrapper.
Xilinx is currently investigating this issue and will update this answer record as soon as a possible workaround is found.
If you are experiencing this problem, open a WebCase and refer to Answer Record 37246:
http://www.xilinx.com/support/clearexpress/websupport.htm Revision History 08/04/2010 - Initial Release