(Xilinx Answer 30212) Spartan-3AN - Known issues with In-System Programming (ISP) of the Spartan-3AN via SVF files
(Xilinx Answer 31794) Platform Flash XL, EDK Support - How do I access the Platform Flash XL from an EDK design?
(Xilinx Answer 32653) Spartan-3/-3E/-3A/-3AN/-3DSP Families - I/Os glitch during power up or down, or a PROG_B pulse
(Xilinx Answer 16829) Virtex and Spartan FPGAs - How does the JTAG JPROGRAM instruction work?
(Xilinx Answer 3684) FPGA Configuration: DONE Pin does not go HIGH...
(Xilinx Answer 11433) JTAG - Do the JTAG pins need external pull-ups? What should I do with unused JTAG pins?
(Xilinx Answer 3203) JTAG - General description of the TAP Controller states
(Xilinx Answer 33575) Spartan-6 FPGA - JTAG Configuration Setup For Designs Using GTPs
(Xilinx Answer 30037) iMPACT 9.2.04i - Spartan-3AN Starter Kit board, JTAG programming fails
(Xilinx Answer 16832) JTAG - What is a JTAG scan bridge, scan path linker, or JTAG multiplexer/JTAG mux?
(Xilinx Answer 8265) JTAG BSDL - What is the format of the IDCODE for Xilinx devices?
(Xilinx Answer 34032) Config - What is the relationship between the TCK output and clock input frequencies for XAPP424?
(Xilinx Answer 44942) Virtex-7, Kintex-7, Artix-7 FPGA Configuration - BUSY Pin Removal
(Xilinx Answer 44237) 13.3 - Bitgen - 7 Series - DonePipe option is now enabled by default
(Xilinx Answer 42543) 7 series Configuration - Fallback is disabled by default; Multiboot image does not fallback
(Xilinx Answer 43174) 7 series - PROGRAM_B pin held Low prior to power-up does not delay configuration
(Xilinx Answer 42544) 7 series Configuration - When Fallback is enabled, the device status register is always cleared after a failed configuration attempt
(Xilinx Answer 42128) FPGA Configuration - How many clock cycles should I apply to CCLK after DONE has gone High?
(Xilinx Answer 41782) 7 series - Why is there no longer a recommendation for Thevenin termination on the CCLK pin for configuration?
(Xilinx Answer 41298) SelectIO 7 series - What power rail supplies the dedicated configuration pins? (MODE pins, JTAG pins etc.)
(Xilinx Answer 47449) Virtex-7 XC7VX690T Initial Engineering Sample (IES) - iMPACT Verify fails and Configuration Readback does not work correctly unless PCIe DRP is instantiated
(Xilinx Answer 50163) Tandem PROM - What signals are added to my design by using the Tandem PROM solution?
(Xilinx Answer 50489) 7 Series - ERROR:Bitgen:145 - Why are RS0 and RS1 pins persisted if the design is not using Multiboot and the bitgen ConfigFallback option is not set?
(Xilinx Answer 40212) Configuration FPGA Multiboot - Can I multiboot a master and slave device at the same time in a parallel or slave daisy chain?
(Xilinx Answer 51337) 7 Series - How can I work around the Fallback limitation for 32-bit addressing in SPI mode?
(Xilinx Answer 51473) 7 Series - Which dual mode configuration pins do the "Bitgen -g persist:yes" option apply to on 7 series devices?
(Xilinx Answer 51479) 2012.x Vivado - How can I generate a bin file in the Vivado tool?
(Xilinx Answer 51753) ZC702 - Temporary Deviation of QSPI PROM Devices on Revision 1.0 Evaluation Boards
(Xilinx Answer 51775) Zynq - What is the max QSPI frequency for (x1,x2,x4,x8) modes?
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs, flash access is always in BPI Asynchronous Mode
(Xilinx Answer 52626) 7-Series - STARTUPE2_USRCCLK0 ignores first two clock cycles at output
(Xilinx Answer 52660) 2012.3 - QSPI PROM files created from Vivado bitstreams fails to program FPGA