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AR# 37271

12.2 EDK - ML605 BSB design uses P30_CS_SEL rather than FPGA_FCS_B as CE of BPI Flash

Description


According to the ML605 Board User Guide and Schematic, the P30_CS_SEL (AJ12) signal is used to select between platform flash or BPI flash, and the FPGA_FCS_B signal (Y24) should be used as Chip Enable.
However, in the BSB design, the Mem_CEN output from the xps_mch_emc IP is inverted with an util_vector_logic IP, and then the inverted signal is locked to pin AJ12 in UCF.
Why is this the case?

Solution


The interpretation about the P30_CS_SEL and FPGA_FCS_B is correct. However, the BSB design works too.
By default, the unused pinsare tied to ground by BitGen. Since the FPGA_FCS_B pin (Y24) is not used in the BSB design, it is always "0". So, when the BPI Flash is selected by P30_CS_SEL, itis enabled too.
The BSB design can also be modified to use FPGA_FCS_B as Chip Enable signal. For example, modify the design as follows:

In MHS:

PORT fpga_0_FLASH_CE_inverter_Res_pin = net_vcc, DIR = O
PORT FPGA_FCS_B = net_bsbassign0, DIR = O

BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MEM0_WIDTH = 16
PARAMETER C_MAX_MEM_WIDTH = 16
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TWC_PS_MEM_0 = 11000
PARAMETER C_TWP_PS_MEM_0 = 70000
PARAMETER C_TLZWE_PS_MEM_0 = 35000
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0x8c000000
PARAMETER C_MEM0_HIGHADDR = 0x8dffffff
BUS_INTERFACE SPLB = mb_plb
PORT RdClk = clk_100_0000MHzMMCM0
PORT Mem_A = 0b0000000 & fpga_0_FLASH_Mem_A_pin_vslice_7_30_concat & 0b0
PORT Mem_CEN = net_bsbassign0
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN_pin
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN_pin
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ_pin
END

In UCF:

Net fpga_0_FLASH_CE_inverter_Res_pin LOC=AJ12 | IOSTANDARD=LVCMOS25;
Net FPGA_FCS_B LOC=Y24 | IOSTANDARD=LVCMOS25;
AR# 37271
Date Created 08/05/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 LXT
Tools
  • EDK - 11.1
  • EDK - 11.2
  • EDK - 11.3
  • More
  • EDK - 11.4
  • EDK - 11.5
  • EDK - 12.1
  • EDK - 12.2
  • EDK - 12.3
  • Less
IP
  • XPS Multi-CHannel External Memory Controller
Boards & Kits
  • Virtex-6 FPGA ML605 Evaluation Kit