UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37277

FPGA Editor 12.2 - Unable to reroute GT signals

Description


I am unable to reroute my GT signals using FPGA Editor. 

When I try to add a new signal to a GT pin after I have deleted the old one, I receive the following DRC error when I try to generate the bit file or run DRC check:

ERROR:PhysDesignRules:1709 - Incomplete connectivity. The pin <xxx> of comp block <xxx/xxx/gtp_dual_i> is used and partially connected to network <xxx>. All networks must have complete connectivity through out the comp hierarchy and the connectivity for this pin must be removed or completed.


Why am I getting this error and how do I work around this? 

Solution


The issue is that the internal connection from the GTP Slice does not connect to the GTP block. 

You can confirm this by clicking into the GTP Slice where the signal from the slice input to the block will not be connected. 

This is a bug in FPGA Editor 12.1/12.2 and has been fixed for FPGA Editor 12.3. 

To work around this issue, in the GTP Slice make an edit either to another signal where a PIP is available or change one of the block attributes. 

For example, change RXUSRCLK21 to use the opposite edge and then back again. 

After making the change, apply the changes. 

This will cause FPGA Editor to re-examine the block and connect the slice input to the block. 
AR# 37277
Date Created 08/05/2010
Last Updated 09/10/2014
Status Active
Type Known Issues
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2