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AR# 37288

14.x Constraints - How do you constraint source synchronous data and clock?

Description

How do you constraint source synchronous data and clock?

Solution

For inputs, OFFSET IN VALID can be used to denote the phase relation between data and clock.
For outputs, OFFSET OUT with REFERENCE_PIN can be used to verify the phase relationship between clock and data.

Xilinx recommends using the register in the I/O Logic, to insure the relationship between clock and data stays constant. A PLL generated clock can be used to phase shift the clock to meet timing and adjust the phase relationship.

AR# 37288
Date Created 12/05/2012
Last Updated 12/05/2012
Status Active
Type General Article
Tools
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  • ISE Design Suite - 13
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