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AR# 37323

14.x - Timing - How can I resolve Component Limit Switching error?


How can I resolve Component Limit Switching (CSL)error?


Checking the validity:
- Use printdelays
- Use Delay reporter or FPGA Editor to get the configuration of the component
- Use the latest tool version available

If the CSL is valid, it means that the design should be changed so that the violation no longer occurs,for instance, by a change in the frequency at which a clock is running.
AR# 37323
Date Created 01/17/2013
Last Updated 01/17/2013
Status Active
Type General Article
  • ISE Design Suite - 14