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AR# 37324

System Generator 12.2 - Ethernet HW-CoSim fails timing for ML605 board

Description

Timing failures can be seen for some designs when attempting to generate the Ethernet HW-CoSim block for the ML605 board using System Generator 12.2.

Solution

The workaround is to place a TIG constraint on one of the Ethernet cosim paths as timingneeds to be checked on this path. Please add the following constraint toeth_cosim_top.ucf:

NET "*emac_speed_is_10_100" TIG;

Eth_cosim_top.ucf can be located in your ISE installation area.For example:

C:\Xilinx\12.2\ISE_DS\ISE\sysgen\plugins\compilation\Hardware Co-Simulation\ML605\Ethernet\Point-to-point

or

$XILINX/sysgen/plugins/compilation/Hardware Co-Simulation/ML605/Ethernet/Point-to-point
AR# 37324
Date Created 09/21/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
Tools
  • System Generator for DSP - 12.2