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AR# 37327

12.2 Virtex-6 MAP - Patch available to restore 12.1 register ordering behavior


A change in the register ordering behavior of Pack has been found to cause QOR regressions in some Virtex-6 FPGA designs.The regression can appear as either a timing issue or a routability issue.
Register ordering is a structured placement algorithm that causes FFs from the same bus to be packed together in the same slice component in sequence. The behavior in ISE Design Suite 12.1 was to pack 8 FFs together in the same slice. This "compact bus packing" leads to a high number of LUT route-thrus being reported in the device utilization summary of the map report, causing some concern that this was a source of device congestion. A decision was made to change the register ordering to a four FF per slice structure. This change has been found to have a negative impact on some designs, so a patch has been made available to restore the 12.1 behaviorof 8 FFs per slice.


A patch is available to restore the 12.1 register ordering behavior in 12.2 for all platforms:
To install permanently, unzip the patch in the XILINX install directory while maintaining directory structure.
To install temporarily,unzip the patch in an empty directorywhile maintaining directory structure. Set the MYXILINX environment variable to that directory to use the patch. Unset the variable to remove the patch and use the original 12.2 behavior.
AR# 37327
Date Created 08/13/2010
Last Updated 12/15/2012
Status Active
Type General Article