The Fmincal specification is a requirement for the IODELAY2 in Variable Mode based on the longest bit period that the taps can calibrate to. For SDR data rates, the bit period is equal to the clock period, so the clock frequency can be 188 Mhz (5.3nS bit period). If using DDR, then the bit period is half of the CLK period, so the clock frequency can be as low as 94 Mhz and still meet the requirements of 5.3nS bit period.