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AR# 37414

Virtex-6 GTH Transceiver - Attribute updates for ES silicon

Description

For ES silicon, port and attribute updates need to be made to the GTH wrapper generated by the GTH Wizard to ensure reliable operation.This answer record describes which attributes need to be updated and the values to which they need to be set.

Solution

Theattribute and port updatesnoted below can be generated natively by the Virtex-6 FPGA GTH Wizard v1.6 whichwas officially released with ISE Design Suite12.4.For an earlier version of this core, you can use the following ZIP file:
http://www.xilinx.com/txpatches/pub/applications/misc/gth_initialization_patch.zip

To use this patch, first unzip the files to a location of your choice, generate an environment variable called MYXILINX and set it to the location of the /rtf directory that is to be generated.For additional information on this variable and its use, see (Xilinx Answer 2493).

Attribute and port updates that need to be made in the GTH wrapper for ES silicon:


Attribute

Value

PLL_CFG0[15:6]

27Fh(1)

PLL_CFG1

81C0h

DLL_CFG0

8262h

MISC_CFG

0008h

RX_CFG0_LANE<n>

0500h

RX_CFG1_LANE<n>

821Fh

RX_CFG2_LANE<n>

1000h


RX_CTLE_CTRL_LANE<n>

00FFh

RX_CDR_CTRL1_LANE<n>

4200h

RX_PI_CTRL0

63F0h

TERM_CTRL_LANE<n>

5007h

TX_CFG0_LANE<n>

203Dh

TX_PREEMPH_LANE<n>

00A1h

PCS_MISC_CFG_0_LANE<n>

1116h when TXRATE = 2'b00
1117h when TXRATE = 2'b01

1114h when TXRATE=2'b10

1114h when TXRATE=2'b11



LANE_PWR_CTRL_LANE<n>

0400h

RX_LOOP_CTRL_LANE<n>

007Fh

RX_AEQ_VAL0_LANE<n>

0182h

RX_AEQ_VAL1_LANE<n>

0836h

RX_AGC_CTRL_LANE<n>

[15:6]: Reserved, tie to 10'h0

[5]: AGC manual enable (always set to 1)

[4:0]: AGC manual value (depends on transmit signal amplitude and channel loss)

For swing of 770 mV PPD and channel loss ~2 dB, set AGC manual value to 5'h0

For each 40 mV loss of amplitude below 770 mV, increase the AGC manual value by 1

For each dB of channel loss beyond 2 dB, increase the AGC manual value by 1
TX_CFG1_LANE<n> 0D83h
TX_CLK_SEL1_LANE<n> 2121h
TX_CFG2_LANE<n> 0081hwhen TXRATE = 2'b00
0001h for other values of TXRATE

Notes:
  1. Bits [5:0] representthe feedback divider of the PLL inthe GTH Quad, which should be set based on the recommendations in the GTH User Guide (UG371), see the "PLL Settings for Common Protocols" section.
Attribute
PMA Loopback

Other modes

(DEFAULT)

PMA_LPBK_CTRL_LANE<n>[1:0]

2b10
2'b00
SLICE_CFG

0003h
0000h
LANE_AMON_SEL
0100h
00F0h


Quarter Rate Mode with TX_FABRIC_WIDTH = 16 or 20:

Port

TX_FABRIC_WIDTH = 16

TX_FABRIC_WIDTH = 20

TXRATE/RXRATE

2'b10

2'b10

SAMPLERATE

3'b000

3'b000

PLLPCSCLKDIV

6'h1F

6'h27

Linked Answer Records

Associated Answer Records

AR# 37414
Date Created 08/12/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 HXT
IP
  • Virtex-6 FPGA GTH Transceiver Wizard