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AR# 37433

Xilinx PlanAhead Design Assistant - Errors and Warnings while running DRC during Pin Planning


This portion of the Design Assistant will assist you with resolving errors and warnings that you receive while running DRCs during Pin Planning within PlanAhead.

Note: This Answer Record is a part of the Xilinx PlanAhead Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Solution Center to guide you to the right information.


See (Xilinx Answer 34995) for error I/Os placed on disallowed sites - Single ended global clock terminal mii_tx_clk drives a global clock buffer. For proper functioning, this terminal needs to be placed on the P side of a differential package pin. This terminal, placed at C9, violates this requirement

See (Xilinx Answer 32842) for errorDRC error - Terminal is single ended but has an I/O std of LVDS_25 which can only support differential.
AR# 37433
Date Created 08/20/2010
Last Updated 12/15/2012
Status Active
Type General Article