37465

This section of the Design Assistant provides more information on messages which occur when importing timing results.

Note: This Answer Record is a part of the Xilinx PlanAhead Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Solution Center is available to address all questions related to PlanAhead. Whether you are starting a new design with PlanAhead or troubleshooting a problem, use the PlanAhead Solution Center to guide you to the right information.

See (Xilinx Answer 31909) for "ERROR:importing trce results: No valid paths found for displaying."

AR# 37465
Date Created	08/20/2010
Last Updated	12/15/2012
Status	Active
Type	General Article

AR# 37465 Xilinx PlanAhead Design Assistant - Errors and Warnings while importing Timing Results

Description

Solution

Actions

All Programmable Technologies and Devices

New Connectivity Kit for High-Bandwidth and High-Performance Applications

Mobile Access for Forums

Kintex-7 FPGA KC705 Evaluation Kit

All Programmable Technologies and Devices

AR# 37465 Xilinx PlanAhead Design Assistant - Errors and Warnings while importing Timing Results

Description

Solution

Actions