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AR# 37470

12.2 TRCE - Paths covered by PERIOD constraints are showing as unconstrained, why?

Description

I have a path from a Flip-flop (FF) to another FF in my design and the source and destination are both members of the same (or even of related) PERIOD constraints.

However, the path between them shows as unconstrained.

Why am I seeing this behavior?

Solution

This problem is generally associated with the source and/or destination being a member of multiple time groups. 

When a component is a member of multiple time groups and is used in different PERIOD specification, then TRCE does not know which constraint to use.

For instance, if you have FFA as the source and FFB as the destination, you can add FFA and FFB to the CLKA time group:
 

NET "CLKA" TNM_NET = CLKA;


You can also add FFB to the CLKB time group (as if CLKB is driving the CE pin):

NET "CLKB" TNM_NET = CLKB;


Now define the PERIOD constraints:

TIMESPEC TS_CLKA = PERIOD "CLKA" 10 ns;
TIMESPEC TS_CLKB = PERIOD "CLKB" 20 ns;

Below is what you could expect to see in the PCF:

TIMEGRP CLKA = BEL "FFA" BEL "FFB";
TIMEGRP CLKB = BEL "FFB";
TS_CLKA = PERIOD TIMEGRP "CLKA" 10 ns HIGH 50%;
TS_CLKB = PERIOD TIMEGRP "CLKB" 20 ns HIGH 50%;


The PERIOD constraint on CLKB is not related to CLKA. 

TRCE has no indication if it should use the CLKA or the CLKB PERIOD constraint when looking at this cross-clock domain analysis.

If TRCE uses the TS_CLKA constraint on both FFA and FFB, then this path will be covered.

However, if TRCE uses TS_CLKA on FFA and TS_CLKB on FFB, then this path will show as unconstrained.

This is not considered a bug and the tools are working as expected. 

To see the desired analysis the user should only add the components to the correct time groups for cross-clock domain analysis. 

f it is necessary to have the component in multiple time groups, then the PRIORITY keyword can be used, or an additional time group can be added and new more specific constraints added for the cross-clock domain paths.
AR# 37470
Date Created 08/16/2010
Last Updated 12/02/2014
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • ISE Design Suite