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AR# 37474

ISE Simulator (ISim) - Bi-directional port signals appear as undefined "UU"

Description


I have a design that successfully simulates in ModelSim.However, when I use ISim and other 3rd party simulators, I see that bi-directional signals in the design show "UU" instead of the expected result.
How can I resolve this issue?

Solution


This issue can occur if there is ambiguity in the output drivers for inout ports. For example, if the following two entities drive each one bit of a two-bit bidirectional bus (data):

architecture arch_foo of foo is // This is instantiated as U0 in top level
begin
data(0) <= '1';
end architecture arch_foo;

architecture arch_bar of bar is // This is instantiated as U1 in top level
begin
data(1) <= '1';
end architecture arch_bar;

it is ambiguous what the drivers for the whole "data" bus are at the scope of each entity.This results in two drivers on each bit of the bus: one assigning a 'U', the other assigning a '1'.
ModelSim ignores this ambiguity and warns the user of the non-adherence to VHDL standards via the following warning:
# ** Warning: (vsim-8684) No drivers exist on inout port /testbench/u0/a(1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/a(1).
# Region: /testbench

To resolve this issue, make sure that all drivers are defined for inout buses. For example:
architecture arch_foo of foo is
begin
a(0) <= '1';
a(1) <= 'Z';
end architecture arch_foo;

architecture arch_bar of bar is
begin
a(1) <= '1';
a(0) <= 'Z';
end architecture arch_bar;
AR# 37474
Date Created 08/17/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • More
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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