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AR# 37484

CORE Generator - What are the output files generated for an IP core and how they can be used?


What arethe output filesof the CORE Generatortool and how they can be used?


The "flist.txt" file, generated during core generation, gives a complete list of generated files and usage. Following is a partial list indicating some of the most commonly used and accessed files created during generation.

  • XCO - ".xco"is a file that records all the customization parameters used to create the core and the project options in effect when the core was generated. This file can be added into theISE project; the ISE tool uses this file to find proper source files for synthesis and simulation.

  • HDL wrapper files -".v" and".vhd"are simulation files .except for some open source code IP such as PCIe MIG In these cases, ".v" and ".vhd" are synthesizable files.

  • Core netlist - ".ngc" and ".edn" are netlist files. Translation will merge these files into the whole project.A wrapper file of this netlist will beneeded in Verilog as a black box in synthesis.

  • Instantiation templates - ".vho" and ".veo" files aretemplate files for VHDL and Verilog toinstantiatethe generated IP.
AR# 37484
Date Created 04/25/2012
Last Updated 02/13/2013
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 12.1
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