UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37595

Spartan-6 Integrated Block for PCI Express - SIM_DEVICE attribute on RAMB16BWER is not set to "SPARTAN6"

Description

Version Found: 1.1; v2.1

Version Resolved and other Known Issues: See (Xilinx Answer 45702).

The RAMB16BWER primitive recently added an attribute called, "SIM_DEVICE." 

The core is not setting this to "SPARTAN6".

Solution

Add the SIM_DEVICE attribute to the instantiation of the RAMB16BWER primitive in the pcie_bram_s6.v[hd] file.

This is found in the generated core's source directory. 


Add the attribute and set it to "SPARTAN6".

Verilog

RAMB16BWER #(

    .SIM_DEVICE ("SPARTAN6"),

    etc....


VHDL

ramb16 : RAMB16BWER
generic map (
   SIM_DEVICE    => "SPARTAN6",

   etc...



Revision History
01/18/2012 - Updated; added reference to 45072
10/27/2010 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Associated Answer Records

AR# 37595
Date Created 10/26/2010
Last Updated 09/22/2014
Status Active
Type Known Issues
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )