Add the SIM_DEVICE attribute to the instantiation of the RAMB16BWER primitive in the pcie_bram_s6.v[hd] file found in the generated core's source directory. Add the attribute and set it to "SPARTAN6".
Verilog
RAMB16BWER #(
.SIM_DEVICE ("SPARTAN6"),
etc....
VHDL
ramb16 : RAMB16BWER
generic map (
SIM_DEVICE => "SPARTAN6",
etc...
Revision History
01/18/2012 - Updated; added reference to 45072
10/27/2010 - Initial Release
Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 37938 | Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues | N/A | N/A |
| 37939 | Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1 | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45702 | Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions | N/A | N/A |
| 39371 | Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.2 | N/A | N/A |
| 37939 | Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.1 | N/A | N/A |
| 37938 | Spartan-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Release Notes and Known Issues | N/A | N/A |