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AR# 37602

iMPACT 12.2, BPI - "IDCODE not validated while writing FDRI"


The bit file can be programmed into FPGA through JTAG ports successfully. However, with the MCS generated from this bit, I always get the following errors in BPI configuration; FPGA cannot work.

INFO:iMPACT:2492 - '1': Completed downloading core to device.
INFO:iMPACT - '1': Checking done pin....done.
'1': Core downloaded successfully.
'1': Verifying BPI device...
'1': Verification completed successfully.
'1': Configuration data download to FPGA was not successful. DONE did not gohigh, please check your configuration setup and mode settings.
PROGRESS_END - End Operation.
Elapsed time = 157 sec.
INFO:iMPACT - Current time: 24 11:07:13 2010
// *** BATCH CMD : ReadStatusRegister -p 1
Maximum TCK operating frequency for this device chain: 10000000.
Validating chain...
Boundary-scan chain validated successfully.
'1': Reading status register contents...
CRC error : 0
IDCODE not validated while writing FDRI : 1
DCM matched: 1
status of GTS_CFG_B : 0
status of GWE: 0
status of GHIGH : 0
value of VSEL pin 0 : 1
value of VSEL pin 1 : 1
value of VSEL pin 2 : 1
value of MODE pin M0 : 0
value of MODE pin M1 : 1
value of MODE pin M2 : 0
value of CFG_RDY (INIT_B) : 0
DONEIN input from Done Pin : 0
POST_CRC_ERR error : 0
SYNC word not found : 0


The IDCODE invalid error is due to an improper ConfigRate setting.

For Spartan-3A/3AN andSpartan-3A DSP FPGAs, the maximum ConfigRate for parallel flash PROMs is 17 MHz (Tacc/Tavqv <= 18 ns). If CCLK is too fast, BPI cannot communicate correctly with the FPGA and then the IDCODE invalid error will be reported when configuration starts.

Considering the 50% tolerance of CCLK, it issafe to set ConfigRate <= 10 MHz while generating the bit file.
AR# 37602
Date 03/01/2013
Status Active
Type General Article
  • Spartan-3A
  • Spartan-3A DSP
  • ISE Design Suite - 12.2
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