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AR# 3761

A1.4/F1.4 Map - MAP introduces DRC problem: WARNING:x4kdr:82 - Blockcheck: The pin "F1"...


Map introduces DRC problem by configuring a CLB for external
feed back but failing to define the external signal. This
results in warnings about configured CLB pins that have no
signal attached:

WARNING:x4kdr:82 - Blockcheck: The pin "F1" on comp (mapped
physical logic cell) "U18/PWMPHC0_D" is configured to be used
but has no signal attached to it.


This problem is fixed in the latest M1.4 Core Tools Patch
available on the Xilinx Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip

AR# 3761
Date Created 04/09/1998
Last Updated 04/19/2000
Status Archive
Type General Article