UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3767

A1.4 and Modelsim: How to use the OSC4 component with VHDL simulation (Functional and Timing)

Description


Keywords: OSC4, MTI, Modelsim, Model Technology, UNISIM, SIMPRIM, PERIOD,
PERIOD_8M

Urgency: Standard

General Description: If a VHDL simulation of a design containing an OSC4
component is desired using the Model Technology Modelsim simulator, a
PERIOD must be set for the simulation to occur. If a PERIOD for the OSC4
is not set the following error may be issued during simulation:

# ** Failure: *** Error: a positive value of PERIOD_8M must be specified ***
# Time: 0 ns Iteration: 0 Region: /testbench/osc4_instance/internal_osc4


This solution record describes the configuration statement that can be
used in a VHDL testbench to properly specify the PERIOD of the OSC4 for
designs using the internal oscillator.

Solution

1


Functional (UNISIM) Simulation
------------------------------

For a UNISIM OSC4 initialization, add the follwing configuration
statement to your testbench or a seperate file in which you compile after
compiling your testbench:


CONFIGURATION RTL_simulation OF <entity_name_of-testbench> IS
FOR <architecture_name_of_testbench>
FOR <testbench_instance_name_for_design>:<entity_name_of_design>
FOR <architecture_name_of_design>

FOR <instance_name_of_osc4>: osc4 USE ENTITY UNISIM.OSC4(OSC4_V)
Generic map (PERIOD_8M => 125 ns -- 8 MHz
-- ,SEL_F500K => TRUE -- 500 KHz
-- ,SEL_F16K => TRUE -- 16 KHz
-- ,SEL_F490 => TRUE -- 490 Hz
-- ,SEL_F15 => TRUE -- 15 Hz
);

END FOR;
END FOR;
END FOR;
END FOR;
END RTL_simulation;



In the above example:

1. Add to the end of the testbench or in a seperate file that will be
compiled with the testbench.

2. Replace all names in <> with names from design code and testbench.
Insatnce names above refers to the instance names given to the
instantited design in the testbench and instantiated OSC4 component
in the code.

3. Un-comment the lines in the example configuration statement
corresponing to the connected frequecies in the design. Always
keep the 8 MHz (PERIOD_8M) line regardless of whether it is
connected in the design.

4. After successfully compiling the testbench and code, invoke
simulation using the configuration name now:

vsim RTL_simulation

2


Timing (SIMPRIM) Simulation
===========================

For a Post-M1 created netlist such as that used for timing simulation,
the procedure is very similar however the configuration statement
may need to be slightly modified. As with the proceedure for the UNISIM
simulation, the taps (500 KHz, 16 KHz, etc.) being used should be
uncommented.


CONFIGURATION Post_M1_simulation OF <entity_name_of-testbench> IS
FOR <architecture_name_of_testbench>
FOR <testbench_instance_name_for_design>:<entity_name_of_design>
FOR STRUCTURE

FOR <instance_name_of_osc>: osc4 USE ENTITY WORK.OSC4(STRUCTURE)
Generic map (PERIOD_8M => 125 ns -- 8 MHz
-- ,SEL_F500K => TRUE -- 500 KHz
-- ,SEL_F16K => TRUE -- 16 KHz
-- ,SEL_F490 => TRUE -- 490 Hz
-- ,SEL_F15 => TRUE -- 15 Hz
);

END FOR;
END FOR;
END FOR;
END FOR;
END Post_M1_simulation;


The reason for these modifications is that the architecture for the VHDL
netlist produced by M1 is always STRUCTURE. If this does not match the
architecture of the original design, this must be changed. Also, the
simulation model for the OSC4 in now written in the design netlist rather
than existing in the UNISIM library. For this reason, the refernced
library is now WORK rather than UNISIM.
AR# 3767
Date Created 04/10/1998
Last Updated 10/13/1999
Status Archive
Type General Article