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AR# 37679

8.1 Fitter Report - The tools are incorrectly writing the equation for a latch


The 8.1 Fitter Report may incorrectly report the equation for a latch.


In 8.1 CPLDfit may incorrectly write the equation for a latch.

In a very small number of designs it has been seen that the equation of Latch may include an erroneous inverter on the PRE in the VHDL and Verilog report. This is only a reporting issue and the correct logic is implemented.
An example of the issue:

LDCP_aEstopLatch_n: LDCP port map (aEstopLatch_n,'0',NOT aEstop_n,'0',NOT );
Register Legend:

The ABEL report it correct.
q.D = Gnd; // (0 pt, 0 inp)
q.LH = !clkn; // GCK (0 pt, 0 inp)
!q.AP = !orb & !ora; // LPST (1 pt, 2 inp)

To work around this issue use the ABEL report type.
AR# 37679
Date Created 09/15/2010
Last Updated 05/08/2014
Status Archive
Type General Article