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AR# 37680

8.1sp2 CPLDFit - Incorrect connection of CLK Divider output causes a Fatal Error


If the output of the CoolRunner-II CPLD CLK Divider goes to the D input of a flip-flop, a Fatal Error occurs.

FATAL_ERROR:Cpld:xbr_bldclkdiv.c:404:1.15 - CPLD fitter has encountered an error
while processing the Clock Divider component. Most likely the error is due
to an invalid connection of the divided clock output. A divided clock can
only drive the clock input of registers. Process will terminate. To
resolve this error, please consult the Answers Database and other online
resources at http://support.xilinx.com. If you need further assistance,
please open a Webcase by clicking on the "WebCase" link at


Connecting the output of the CoolRunner-II CPLD CLK Divider to anything other than a CLK input of register is not supported.

The user should change the design to connect the CLK Divider output to only clock inputs.
AR# 37680
Date Created 09/15/2010
Last Updated 05/08/2014
Status Archive
Type General Article