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AR# 37681

8.2.01i ISE - The Abel design is not converted to VHDL correctly

Description

During the synthesis phase of an Abel design, the Abel is converted into VHDL in the .VHF file. In one design it was found that the conversion was not correct.

Solution

A bi-directional signal during the conversion was defined as an out.

To work around this issue you can open the .vhf file and change the type to inout.

Abel is no longer supported in newest version of ISE software.
AR# 37681
Date Created 09/15/2010
Last Updated 05/08/2014
Status Archive
Type General Article