An issue was found with the MIG v3.5 Spartan-6 FPGA MCB design when the C_SIMULATION parameter is set to FALSE. This parameter is used to skip portions of the initialization process to speed up simulation run time. By default, the MIG design sets this parameter to TRUE in the generated testbench (sim_tb_top) and to FALSE in the top-level rtl module (to ensure the initialization process is not abbreviated in hardware).
This issue found in v3.5 causes calibration to not complete (cal_done remains 0) when the C_SIMULATION parameter is set to FALSE in the simulation testbench (default setting is C_SIMULATION=TRUE) for both VHDL and Verilog design. This will additionally affect successful hardware implementation for all VHDL designs. Hardware failures can be seen as calibration failures, data errors, or a random combination of these. Because of this, the update is required for all VHDL designs but is only required for Verilog designs when users wish to run simulation with C_SIMULATION set to FALSE.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 36211 | MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 | N/A | N/A |